Most major segments of the integrated circuit industry have alternate sourcing. For example a purchaser can buy SRAMs, DRAMs, and microprocessors from more than one source (i.e., a company with IC fabrication facilities). Customers have always found it desirable to have alternate sourcing available for an assured supply and lower cost by virtue of the competition among the alternate sources.
In the early eighties, the leading ASIC vendors were vertically integrated, i.e. they provided the three key technologies required for successful ASICs. These key technologies are the CAD (Computer Aided Design), the ASIC technology (The ASIC products itself; the methodologies for design, simulation, and test; and guaranteeing that the silicon works to customer specifications), and the silicon fabrication facilities to manufacture the ASICs. These ASIC vendors guaranteed the ASICs would function properly and reliably only if the ASICs were produced using that vendor's CAD, ASIC Technology, and silicon fabrication facilities and process.
Thus, in this prior art system, once a customer decides on a specific ASIC vendor, the customer is locked into using and relying on that ASIC vendor. Once the ASIC goes to production the customer is dependent on that single silicon fabrication source. Any problems with this fabrication facility, process, or company will directly impact the production of the ASICs, upon which the customer's systems are based. In such a situation the customer can go to another ASIC vendor to obtain a newly designed ASIC chip to serve the same purpose, but this is costly, time consuming, and the newly designed ASIC chip may not perform the same.
In the mid 1980's CAD companies, such as Cadence, took advantage of the customer's desire for alternate sourcing by offering a set of CAD tools that offered the customers some independence from the ASIC vendors, as their CAD tools were suitable for use with any number of ASIC vendors. Customers quickly embraced this "open" CAD concept.
This open CAD concept was a step in the direction of alternate sourcing ASICs, but ASIC vendors still required the use of their specific ASIC Technology which was integrated to their silicon fabrication process. The precise timing models in the library of ASIC technology must represent the behavior of the ASIC devices when fabricated by the ASIC vendor. An ASIC vendor is only able to guarantee accurate timing in the ASICs manufactured by themselves, and cannot guarantee the ASIC will function the same if it is fabricated using another vendor's ASIC technology or fabrication process.
For many years, ASIC vendors have been porting libraries of their proprietary ASIC products to various software tools available from different CAD companies. This provides the systems designer with a wide choice in these front end tools. However, this approach does not provide the flexibility of allowing the systems designer to choose different semiconductor fabrication facilities and guarantee the same high performance, and in some cases even the same functionality, since different vendors, different fabrication processing techniques, etc. result in variations in device performance.
As in any market, customers desire an "alternate sourcing" of their ASICs. Today there is no method or system for the true alternate sourcing of ASICs. There have been attempts to provide alternate sourcing of ASICs by two ASIC vendors teaming up to second source products using as identical ASIC architecture and fabrication processes as possible. However, even in these instances where two or more vendors are actively pursuing identical fabrication techniques in each of their fabrication facilities, fabrication processes change over time due to different product priorities, yield enhancement techniques, use of different manufacturing equipment, etc., and thus device performance variations will increase over time. None of these attempts to second source ASICs have worked well over time. So, in spite of good intentions, alternate sourcing quickly becomes incompatible.
In array based products, such as gate arrays and embedded arrays, alternate sourcing generally does not exist. The main technical reason is the large number of macrocell library elements, which could number more than 100. These are based on a fixed primitive cell with predetermined transistor widths. It is impractical for a designer to adjust the width of each transistor to compensate for performance differences of different semiconductor processes for all the macrocells in the library. This is the main technical reason that alternate sourcing in ASICs does not exist. The only possible exception is if two companies agreed on the same architecture, library, design, methodology, design tools, same place and route software and methodology, and same semiconductor process technology. Because of customer insistence, there have been such attempts at alternate sourcing. However, different companies have different priorities and the semiconductor process technology tends to quickly drift apart and the alternate sourcing begins to fail.
At present, when a second source is needed, systems companies have no choice but to do an almost total redesign of the ASIC. Even then the ASIC components obtained from two separate ASIC vendors may or may not work the same on the customer's systems. The problem is that the second vendor's ASIC has a different architecture, different library elements, different timing performance, different methodology, different place and route, as well as a different fabrication process. The success rate of second sourcing leaves a lot to be desired.
In order to develop confidence that an ASIC will perform as desired or expected, the designer needs to perform accurate gate level simulation, including timing. Since each ASIC vendor has libraries with different timings and possibly different functional library elements, the systems customer now must select one ASIC vendor to which the simulation will be directed. Once the ASIC vendor selection is made, the simulation, place and route, timing adjustments for wire routing, and manufacturing will take a significant amount of time and effort. It is costly for the customer to duplicate this time and effort for an alternate source. The customer is in effect, due to time and cost constraints, locked in a sole sourced situation, meaning the customer can only buy from this one ASIC vendor.
In order for a customer to obtain a second source, the customer needs to duplicate the simulation on a different library, perform a different place and route which will provide different wire induced delays, and manufacture the gate array (generally a different architecture) on a different fabrication process. The odds are not good that the second sourced ASIC device will work the same after going through so many steps, each of them different from one another.
This situation increases the cost of the ASICs, but more importantly, a single source may not be able to meet demand. A single sourced vendor could have a yield problem resulting in an insufficient supply of ASICs, which in turn may stop production of the customer's electronic system which incorporates the ASIC. Or if the system sells much better than expected, a single source vendor most likely will not be able to increase production quickly enough to meet the customers demand for the ASICs.
FIG. 1A is a flow chart of a prior art attempt to provide alternate sourcing of a given basic circuit design from a plurality of vendors. As shown in FIG. 1A, a first step 201 is to define a device specification, including the system behavior and timing desired. Step 202 is a synthesis step, during which equivalent logic is synthesized into different libraries of different alternate sources. This results in a netlist for each source's library which is simulated for timing and functionality in steps 203-1 and 203-2. The results of step 202 are suitable for application to a plurality of ASIC vendors parameters, by simulation steps 203-1 and 203-2, in order to verify by simulation of gate level implementations of the specified functionality and timing specifications the expected operation of ASIC devices produced by each vendor. These simulation steps need to be done at least once per vendor because the primitive library elements are logically different and have different speeds.
This prior art also requires a duplication in the place and route steps 204-1 and 204-2, during which devices and interconnects are defined in accordance with each vendor's parameters. Place and route must be uniquely performed for each ASIC vendor in steps 204-1 and 204-2 because this step significantly impacts timing. Most likely the two vendors use different place and route algorithms. So step 204-2 must be redone until the timing can match the timing of the first source which utilized a different place and route step 204-1. Fabrication steps 205-1 and 205-2 are then performed by each vendor, in accordance with specific layout steps performed for that vendor. Thus, it is shown in the prior art flow chart of FIG. 1A that a number of steps required in order to allow each ASIC vendor to fabricate devices which are intended to be functionally identical are not themselves identical, and due to the variations in these steps are likely to lead to supposedly functionally identical ASICs from two vendors which, unfortunately, are all too often not as functionally identical as one would need or desire. For example, simulation steps 204-1 and 204-2 are performed according to the individual vendor parameters, and place and route algorithms result in a difference in location of various devices within each ASIC and different electrical interconnect lengths as well. Thus, in addition to the fact that a number of steps must be duplicated specifically for each vendor, the net result is a set of devices available from a plurality of vendors which all too often have significant disparities in operating characteristics.
The other approach to seeking a plurality of foundries for alternate sourcing is to recognize the performance difference of different foundries. Each foundry's performance can be depicted in the propagation delay, tpd, of a gate. This distribution is gaussian, and has a minimum and a maximum propagation delay, as shown in FIG. 1B. If we include the gaussian distributions of two foundries in one graph, as shown in FIG. 1B, we can take the smallest of the two minimum delays and call it the lower limit of both processes Tpd(min A+B). We can also take the largest of the two maximum delays and call it the upper limit of both processes Tpd(max A+B). These new lower limit and upper limit delays are the new minimum and maximum delays of a larger performance window for the combined delay distributions. We can now specify that a given gate's delay shall be within this new performance window which is larger than either performance window of source A or source B. Then a library is generated with this wide performance window. The system customer now needs to make sure his ASICs will operate over a larger performance window. He needs to guarantee that his chip will work in his system when a chip happens to have the slowest performance, the Maximum delay Tpd(max A+B), in the combined performance window. He also needs to guarantee that another chip which may have the highest performance, Minimum delay Tpd(minA+B), in the combined performance window will work the same way. This may mean that he needs to slow the system performance, making his product less competitive. At the other extreme there is higher performance. Higher performance means more power consumption. The higher maximum performance, minimum delay, may mean the need for larger heat sinks or fans to cool the ASICs, which make the system heavier and more costly, and will increase power consumption, which may lead to larger battery requirements if it is a portable system. So with this approach, a penalty is paid in power consumption and yet the system has to run at a lower speed.